Tutorial 1A

Time: 2022/10/28 08:30-10:10

Room: Room A

Title: Design of Low-Power PLL and CDR Integrated Circuits for High Speed Wireless/Wireline Communication

Speaker: Zhao ZHANG, Institute of Semiconductors, Chinese Academy of Sciences, China

Abstract: To further increase the data-rate of the 5G wireless transceiver (e. g. > 10Gb/s), an ultra-low-jitter phase-locked loop (PLL) with sub-100-fs integrated jitter and low power consumption is required to generate a clean LO signal. This significantly challenges the PLL design. Meanwhile, the four-level pulse-amplitude modulation (PAM4) clock-and-data recovery circuit (CDR), which is the key sub-system of the PAM4 transceiver, is usually more power-hungry due to the more complicated circuit topology.

In this tutorial, we firstly give a brief review of the basics and design considerations of the low-jitter & low-PLL and PAM4 CDR. Then, several recently reported design techniques are introduced to show the development trend. Finally, several low-power design techniques of the ultra-low-jitter PLL and PAM4 CDR are introduced based on our recent research results.

Biodata: Dr. Zhang received the Ph.D. degree from the Institute of Semiconductors, Chinese Academy of Sciences, Beijing, in 2016. From 2016 to 2018, he was a Post-Doctoral Fellow with The Hong Kong University of Science and Technology, Hong Kong. From 2019 to 2020, he was an Assistant Professor with Hiroshima University, Higashi-Hiroshima, Japan. In 2020, he joined the Institute of Semiconductors, Chinese Academy of Sciences, where he is currently a Full Professor. His research interests include the design of low-jitter and low-power PLLs, energy-efficient wireline transceivers, and ultra-low-voltage ultra-low-power analog ICs. He (co)authored more than 50 conference and journal papers, including ISSCC, VLSI, A-SSCC, JSSC, TCAS-I, TCAS-II, TVLSI and etc. He is the TPC member of ICTA, APCCAS, ICCS, and serves as the session chair of ICTA, ICCS, MWSCAS, etc. He is the guest editor of IET Electronics Letters.

Tutorial 1B

Time: 2022/10/28 08:30-10:10

Room: Room B

Title: Memristive devices for analog computing

Speaker：Peng LIN, Zhejiang University, China

Abstract: The recent success of artificial intelligence (AI) is largely powered by deep learning. However, deep learning requires a data-driven approach for building network models, which has become a challenge to run on conventional computers with segregated processing and memory units. In this tutorial, I will introduce the resurgence of analog computing using memristive devices. The tutorial will be divided into three main sections including devices, arrays and applications, featuring device optimization methods, large-scale passive and active array integration, and system implementations for deep learning applications.

Biodata: Dr. Peng Lin is a tenure-track research professor in the College of Computer Science and Technology at Zhejiang University. He received his PhD in Electrical and Computer Engineering from University of Massachusetts Amherst in 2017 and was a Postdoc Associate at Massachusetts Institute of Technology (MIT) from 2017 to 2020. His current research focuses on neuromorphic computing devices and systems. To date, Dr. Lin has published more than 40 papers in peer-reviewed journals and conferences such as Nature Electronics, Nature Nanotechnology, Nature Machine Intelligence etc.

Tutorial 2A

Time: 2022/10/28 10:20-12:00

Room: Room A

Title: Joint Radar-communication CMOS Transceiver: From System Architecture to Circuit Design

Speaker: Wei DENG, Tsinghua University, China

Abstract: Recent years, millimeter-wave and Terahertz radar systems for sensing and radio systems for communication have attracted substantial attention both from the academia and industry. In addition, there is an increasing demanding for fusing both the hardware platform and frequency band of the radar and radio system, which has advantages of energy efficiency, performance optimization, spectrum sharing/efficiency, compact size, interference management, and the overall cost, as compared to assembling of two distinct systems. This tutorial will introduce the current and future trends in the emerging joint radar-communication CMOS transceiver from system architecture to circuit design.

Biodata: Wei Deng received the B.S. and M.S. degrees from the University of Electronic Science and Technology of China (UESTC), China, in 2006 and 2009, respectively, and the Ph.D. degree from the Tokyo Institute of Technology, Japan, in 2013. He was with Apple Inc., Cupertino, CA, USA, working on RF, mm-wave, and mixed-signal IC design for wireless transceivers and Apple A-series processors. Currently he is with Tsinghua University, China, as an associate professor. His research interests include RF, mm-wave, terahertz, and mixed-signal integrated circuits and system. He has authored or co-authored more than 120 IEEE journal and conference articles. Dr. Deng is a Technical Program Committee (TPC) Member of ISSCC, VLSI, CICC and ESSCIRC. He has been an Associate Editor (AE) of the IEEE Solid-State Circuits Letters (SSC-L).

Tutorial 2B

Time: 2022/10/28 10:20-12:00

Room: Room B

Title: Design of Integrated Circuits for High Temperature Applications

Speaker: Yimeng ZHANG, Xidian University, China

Abstract: Working temperature of conventional integrated circuit based on silicon are usually below 125℃. However, ICs are also required in high temperature environment such as oil well, and aircraft engine. This tutorial will start with a brief introduction of semiconductor physics to review why ICs fails at high temperature. Then several mainstream methodologies for high temperature application IC design will be introduced.

Biodata: Yimeng Zhang received the B.S. degree from Tsinghua University, China, in 2005, and the M.S. and the Ph.D. degrees from Waseda University, Japan in 2007 and 2012, resepctively.. He is now a professor of School of Microelectronics, Xidian University, China. His research interests include high temperature IC design and power management IC design. He has published over 30 papers, and has over 20 granted patents.

Tutorial 3A

Time: 2022/10/28 14:00-15:40

Room: Room A

Title: Overcoming the Transimpedance Limit: A Tutorial on Design of Low-Noise TIA

Speaker: Dan LI, Xi’an Jiaotong University, China

Abstract: Noise is probably the single most important performance metric of the high-speed transimpedance amplifier (TIA), which directly sets the sensitivity of optical receiver. The transimpedance limit which dictates the maximum achievable transimpedance gain of the TIA also turns out to fundamentally limit the TIA noise performance. In this tutorial, we analyze and explore two circuit design approaches to overcome the transimpedance limit. The first approach (Type I) realizes a divide-and-conquer methodology to separate the noise-bandwidth problem and solve them individually. The second approach (Type II) employs a multistage stagger-tuned amplifier. Both approaches can overcome the transimpedance limit, forming an effective toolkit for the design of low-noise high-speed TIA for high-sensitivity CMOS optical receivers in current and future applications.

Biodata: Dan Li received Ph.D. degree from University of Pavia, Pavia, Italy, in 2013. From 2007 to 2009 he was with Nvidia Shanghai R&D center, China, where he worked on custom SRAM circuitry. From 2011 to 2014 he was with Studio di Microelettronica, STMicroelectronics, Pavia, Italy, working on CMOS optical receiver for 100GBE optical link and silicon phonics applications. He joined School of Microelectronics, Xi’an Jiaotong University, Xi’an, China, in 2015, where he currently serves as a tenured associate professor. His current research interests include high-speed optical, 3D sensing and low power mixed-signal circuits.

Tutorial 3B

Time: 2022/10/28 14:00-15:40

Room: Room B

Title: Break the Memory Wall: Cross-Layer Co-Design for Energy Efficient AI Processors

Speaker: Chixiao CHEN, Fudan University, China

Abstract: As the great success of artificial intelligence algorithms, machine learning processors are becoming a significant type of high-performance computing chips recently. However, the limited power budget of edge devices cannot support traditional CPU/GPU and intensive DRAM access. The tutorial will cover multiple low power techniques to avoid power-hungry hardware, with emphasis on cross-layer co-design. First, domain-specific algorithm-architecture co-design is discussed and compared with existing SIMD/multi-thread HPC architecture. In addition, algorithm-device/circuit co-design is investigated, where analog and mixed-signal computing-in-memory designs are reviewed. Finally, the tutorial will introduce chiplet technology, a new enabler for next generation ML processors, where architecture-package codesign challenges and chances arise.

Biodata: Chixiao Chen, Ph.D, received the B.S. and Ph.D. degrees in microelectronics from Fudan University, Shanghai, China, in 2010 and 2016, respectively. From 2016 to 2018, he was a Post-Doctoral Research Associate with the University of Washington, Seattle, WA, USA. Since 2019, he has been an Assistant Professor with Fudan University. He is currently an associate professor with the Frontier Institute of Chips and Systems, and the director of SKL Integrated Chips Innovation Center, Fudan University. His research interests include mixed signal integrated circuit design and custom intelligent software-hardware co-designs.