Keynote 1

Time: 2022/10/29  08:30-09:10

Room: Room A

Session Chair: Haiding SUN, USTC

Title: The Road for 2D Semiconductor in Silicon Age

Speaker：Peng ZHOU, Professor, Fudan University 

Abstract:

As the feature size of silicon-based integrated circuits (ICs) approaches the physical limit, short-channel effects appear, gate control attenuates, and leakage current increases, which seriously affects transistor performance and causes chip failure. Due to the inherent thickness of bulk silicon, the physical area cannot be further reduced, which restricts the area efficiency of silicon-based ICs. In addition, the speed mismatch between memory readout and logic operation, and the separation of memory and computing units together form the memory wall bottleneck in silicon-based ICs. With unique characteristics, including no dangling bond surface, atomic-level thickness, abundant adjustable energy bands, excellent optical electrostatic properties etc., two-dimensional (2D) materials have the potential to enhance gate control, reduce leakage, improve energy and area efficiency, and realize the integration of perception, memory and computing. This report discusses the roadmap for the fusion of 2D materials and silicon ICs, including alleviating the problems faced by silicon ICs from the application of 2D materials in gate-all-around, memory and logic transistors, and enabling the creation of an all-in-one sensing, memory and computing system. Finally, it provides an outlook on the challenges and promising paths to fusing 2D materials with silicon ICs for large-scale applications.

Biodata:

Peng Zhou is a full professor at the State Key Laboratory of ASIC and system, School of Microelectronics, Fudan University, China. He received his B.S. (2000) and Ph.D. (2005) degrees in physics from Fudan University, China. He has invented a new type Flash memory technology with both high speed and non-volatile, and realized high-area-efficiency single-transistor logic in-situ memory technology, and obtained high-performance storage devices, high-efficiency algorithms and chips. Currently, Professor Zhou is interested in novel high-efficiency and low-power electronic devices based on layered materials, focusing on the application in memory, synaptic electronics, and neuromorphic systems. He has published more than 200 scientific papers on Nature Nanotechnology, Nature Electronics, and Nature Communications etc.

Keynote 3

Time: 2022/10/29  14:00-14:40

Room: Room A

Session Chair: Siyang LIU, Professor, Southeast University

Title: Advanced Packaging for Chiplet

Speaker：Qidong WANG, Professor, Institute of Microelectronics of the Chinese Academy of Sciences; 

Abstract:

As single chip processors have reached their limits, the shift toward multichip design is driven by the challenge of modern chip manufacturing. Multichip design isn’t new, but the idea has surged in popularity in the last five years. To tackle the problems including Memory Wall, Die-size Wall, Power Wall, Function Wall, the chiplet technology is able to deliver the system level integration with higher function density and yet lower cost. Advanced Packaging, as a fundamental manufacturing chassis for chiplet, is prominent in high density integration of dies with significant enhancement of the interconnection bandwidth comparing with traditional packaging techniques. The presentation will cover the current status of advanced packaging technologies, the challenges and trend for the next phase.

Biodata:

Dr. WANG Qidong received his B.S. degree in Electronics Engineering from Southeast University in Nanjing, and Ph.D degree in Microelectronics and Solid-State Electronics from University of Chinese Academy of Sciences, and worked in Varian Lab, Stanford University as a Visiting Scholar. He currently serves as the Director of Packaging and Integration R&D Center in the Institute of Microelectronics of the Chinese Academy of Sciences. He has been the Principle Investigator in multiple National Science and Technology Major Programs, and he is the author of more than 60 internationally referred journal and conference papers and 76 filed patents. His research interests include Heterogeneous Integration, Antenna-in-Package, 2.5D/3D integration, and Advanced Substrate.

Keynote 5

Time: 2022/10/30 08:30-09:10

Room: Room A

Session Chair: Guangwei XU, USTC

Title: Near Ideal GaN Schottky Diode for High Efficiency and High Power Wireless Power Transfer Application

Speaker：Hong ZHOU, Professor, Xidian University, China

Abstract:

A crucial factor of determining the efficiency of the wireless power transfer (WPT) system is the schottky barrier diode (SBD) in the rectifying circuit, which converts the received RF signal into DC power. In order to increase the rectified power and efficiency, the SBD should substantially possess low turn-on voltage (V_on), low junction-capacitance (C_j), low on-resistance (R_on) and high breakdown voltage (BV) [10]. However, due to the fundamental and inherent limitations of those parameters like low V_on, low R_on and high BV, such that it is a challenge for a diode to achieve high efficiency and high power simultaneously. It is desired that the SBD should possess those parameters as ideal as possible so as to embrace the high efficiency and high power at the same time. By engineering the anode region with low work-function metal and enhanced surface passivation, extremely-low V_on and high BV can be achieved. By incorporating this lateral GaN SBD in a well-designed 5.8 and 10 GHz rectifier circuit, an unprecedented combination of high-efficiency and high-power are achieved simultaneously. High RF/DC conversion efficiency (η_RF/DC) of 80% with input power (P_in) of 2.5 W per single diode are demonstrated, showing a significant progress achieved in the WPT system at 5.8 GHz and 10 GHz.

Biodata:

Hong Zhou received his PH. D. degree at May 2017 from Purdue University. From June 2017 to Feb. 2018, he was a postdoc in University of California Berkely. He is a receipt of the Young Talents Program award. He is now a professor in School of Microelectronics, Xidian University. His research focuses on fabrication, electrical and thermal measurement, and modeling of negative-capacitance Si FETs, wide bandgap GaN and ultra-wide bandgap β-Ga₂O₃ and AlN based FETs for both DC and RF applications. He has authored and coauthored more than 100 journal and conference papers and featured by Semiconductor Today, Compound Semiconductor, Electronic Component News et al. His research articles are cited with more than 3400 times. 

Keynote 2

Time: 2022/10/29  08:30-09:10

Room: Room B

Session Chair: Prof. Dixian ZHAO, Southeast University                                      

Title: Wideband CMOS mm-wave circuits design for 5G communications

Speaker：Kai KANG,  Professor, University of Electronic Science and Technology of China 

Abstract:

Since mm-wave frequency bands are adopted in 5G communications, CMOS mm-wave circuits and systems attract tremendous attentions because of its low cost and high integration capability. However, circuits designers have to face to many challenges of CMOS process, such as the high loss substrate, low Q passive devices, high noise, and limited gain and output power. This paper will introduce technique to overcome these difficulties to design high performance wideband building blocks as well as transceiver chipsets for 5G communication.

Biodata:

Kai Kang received the B. Eng degree from the Northwestern Polytechnical University, China in 2002, and the joint Ph.D. degree from the National University of Singapore, Singapore and Ecole Supérieure D’électricité, France in 2008. Dr. Kang was with the Institute of microelectronics, A*STAR, Singapore as a Senior Research Engineer, and with Global foundries as a Principle Engineer, respectively. Since June 2011, he has been a professor at the University of Electronic Science and Technology of China. His research interests are RF and RF & mm-Wave integrated circuits design and modeling of on-chip devices.

Dr. Kang has authored and co-authored over 200 international referred journal and conference papers, and was co-recipient of several best paper awards or best student paper awards in IEEE conference including Silkroad award in ISSCC 2018. He received the National Science Fund for distinguished young scholars.

Keynote 4 

Time: 2022/10/29  14:00-14:40

Room: Room B

Session Chair: Prof. Qiang LI, USETC                               

Title: The Historical Development of Data Converters; and What We Can Do

Speaker：Sai-Weng SIN，Associate Professor, University of Macau, China

Abstract:

Data Converters are one of the key building blocks and the performance bottleneck in the various applications of integrated circuits in our daily life. The development of data converters is the fundamental driving force behind the modern technology of smart mobile devices based on sensors, communication, and artificial intelligence. However, Data Converters, e.g. SAR ADCs, already have a long history; they served as the key to improve human electronics technology even in the long past, modern, and the foreseeable future. This talk will present the historical development of data converters and review the key data converter development trends in the current era and what we can do.

Biodata:

Sai-Weng Sin (Terry) is currently an Associate Professor in the Faculty of Science and Technology, University of Macau, and is the Deputy Director of State-Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China. He has published 1 book entitled “Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters” in Springer, hold 12 patents and over 170 technical journals and conference papers in the field of high-performance data converters and analog mixed-signal integrated circuits.

Dr. Sin is/has been the member of Technical Program Committee/Review Committee Member of IEEE Asian Solid-State Circuits Conference (A-SSCC), International Symposium on Circuits and Systems (ISCAS), Int. Conference on Integrated Circuits, Technologies and Applications (ICTA), etc. He served as an Associate Editors for the IEEE Transaction on Circuits and Systems II – Express Briefs. He was the co-recipient of the 2011 ISSCC Silk Road Award, Student Design Contest Award in A-SSCC 2011 and the 2011 State Science and Technology Progress Award (second-class), China.

Keynote 6

Time: 2022/10/30 08:30-09:10

Room: Room B

Session Chair: Xin SI，Southeast University

Title: Design Highly Efficient RRAM Computing-In-Memory AI Chips Leveraging the Interplay between Device, Circuit, and System

Speaker：Chunmeng DOU,  Professor, Institute of Microelectronics of Chinese Academy of Sciences (IMECAS), China

Abstract:

The ever-increasing computing usage in the era of AI, big data, and Internet of things calls for the relentless pursuit of improving computing energy-efficiency and throughput, in which non-volatile computing-in-memory (nvCIM) can play a significant role by minimizing the data movement. Resistive memory (RRAM), as an emerging memory gradually ramping up into mass production, has become one of the most widely adopted technological platforms to implement nvCIM because of its balanced power and memory window as well as good compatibility with advanced CMOS process. This talk will discuss the major challenges, recent trends, and several technical enablers of developing highly efficient RRAM nvCIM chips emphasizing on the interplay between device, circuit and system.

Biodata:

Chunmeng Dou has received the B.S. degree in Physics from Nanjing University, Nanjing, China, in 2009, and the Ph.D. degree in Electronic and Applied Physics from Tokyo Institute of Technology, Tokyo, Japan, in 2014. Since then, he has worked on developing non-volatile memory in academia as well as industry. In 2018, he joined the Institute of Microelectronics of the Chinese Academy of Sciences, as a staff researcher. He has published more than 40 technical papers on influential journals and conferences, including Nature Electronics, VLSI and IEDM. His current interests focus on technology development and circuit design for emerging memory-based computing-in-memory IPs and accelerators for AI and other high parallelism algorithms.