CMOS Millimeter-Wave Integrated Phased-Array Transceivers 

Abstract: The increasing demand for high-data-rate wireless links has driven the development of high-frequency broadband applications, such as the 5G millimeter-wave (mm-Wave) and the broadband satellite communications (SATCOM). Large-scale millimeter-wave (mm-Wave) integrated phased array is the key technology to enable these upcoming broadband applications. This talk will discuss the design considerations, challenges and trade-offs of mm-Wave integrated phased arrays based on bulk CMOS technology. Important beamforming building blocks are addressed in detail. Design examples of integrated 5G and SATCOM phased arrays are presented from circuit to system levels.

Bio: Dixian Zhao (Senior Member, IEEE) received the Ph.D. degree in electrical engineering from the University of Leuven (KU Leuven), Belgium, in 2015. Since April 2015, he has been with Southeast University, China, where he is currently a Full Professor. He has authored or coauthored more than 100 peer-reviewed journal articles and conference papers, one book, and two book chapters. His current research interests include millimeter-wave integrated circuits, transceivers and phased-array systems for 5G, satellite, radar, and wireless power transfer applications. Dr. Zhao serves as a Technical Program Committee (TPC) Member or the Sub-Committee Chair for several conferences, including the IEEE European Solid-State Circuits Conference (ESSCIRC), IEEE Asian Solid-State Circuits Conference (A-SSCC), and IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA). He also serves as an Associate Editor for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS.

High-Speed Nyquist ADCs

Abstract: High-speed and ultra-high-speed analog-to-digital converters (ADCs) are essential blocks for 5G/6G wireless communication, wireline communication, measuring equipment, etc., which are usually the bottleneck of large-scale systems. Different ADC architectures show different benefits when applied to different speeds and resolutions. This tutorial will cover the analysis of different ADC architectures, including pipeline, successive approximation register (SAR), time interleaving, and time domain. Hybrid strategies between them are also discussed.

Bio: Minglei Zhang (S’16–M’17) received the B.S. degree in microelectronics from Tianjin University, Tianjin, China, in 2011, and the Ph.D. degree in microelectronics from the Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China, in 2017. From 2014 to 2016, he was a Visiting Ph.D. student at the Analog and Mixed-Signal Center, Texas A&M University, College Station, TX, USA. He is currently an Assistant Professor with the State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China. His current research interests include high-speed and energy-efficient data converters.

Frequency Synthesis Techniques and Low Flicker Noise Oscillators Towards Sub-50fs Jitter: A Tutorial

Abstract: A frequency synthesizer of ultralow jitter (e.g., sub-50fs) is a key block to enable 5G/6G wireless and other high-speed communication standards. It relies on the new architectures of frequency synthesizers and low flicker phase noise oscillators (especially in advanced CMOS). In this tutorial, we discuss the basics and recent advancements in low-flicker phase noise oscillators and low-jitter frequency synthesis techniques. It is expected to serve a unified guide on achieving sub-50 fs jitter requirements.

Bio: Yizhe Hu, Professor, University of Science and Technology of China, Hefei, China

Topic: Design Techniques for High-Efficiency Wide-Bandwidth Envelope-Tracking Supply Modulator

Abstract: This tutorial will talk about how to design a high efficiency wide-bandwidth envelope-tracking supply modulator with recent techniques. It will cover the comparisons between different topologies; the switching converter design considerations, especially the recent ones with multi-level, fast-speed and stepping-up-and–down functions; the linear amplifier implementations, especially the bandwidth improvements. Design challenges and state-of-the-arts techniques for 5G communication applications will be given. Finally, the measurement setup will be discussed, providing design guidelines and considerations.

Bio: Xun Liu (Member, IEEE) received the B.Eng. degree in electronic and information engineering from Zhejiang University, Hangzhou, China, in 2011, and the Ph.D. degree in electronic and computer engineering from The Hong Kong University of Science and Technology (HKUST), Hong Kong, in 2017. In 2017, she was a Postdoctoral Fellow with HKUST and an Engineering Intern with the Department of Power Management IC, Qualcomm Technologies, Inc., San Diego, CA, USA. She was a Senior Analog Designer with Qualcomm, Santa Clara, CA, USA, from 2018 to 2021. In 2021, she joined the Chinese University of Hong Kong (CUHK), Shenzhen, China, as an Assistant Professor. Her research interests include power management integrated circuit (IC) and analog IC design, especially in high-frequency dc–dc converters, hybrid power converters, and power amplifier supply modulator design. Dr. Liu has been a member of the International Technical Program Committees of the IEEE International Solid-State Circuits Conference (ISSCC) since 2021. She served as a Session Chair for ISSCC 2022 and ISSCC 2023. She also served on the review committee of APCCAS 2022. She was the recipient of the President Young Scholar Award from CUHK and the Qualcomm Patent Award in 2020. She was a corecipient of the ASP-DAC University LSI Design Contest Special Feature Award in 2018.

Title：Design of Computation-in-Memory Circuits Based on SRAM

Abstract: Computation-in-Memory (CIM) has emerged as the most promising solution to tackle the Memory-wall problem in traditional von Neumann architecture. Numerous silicon verified CIM macros have been proposed for AI edge and cloud devices. This informative tutorial provides a comprehensive overview and comparison of recent SRAM based CIM circuits. Beginning with an introduction to the latest AI algorithms for computer vision and image processing applications, which have served as the basis for numerous AI hardware designs, the tutorial proceeds to present a survey of typical SRAM CIM circuits utilizing various computing methods, including charge, voltage, current, time, and digital domain. Key trade-offs of both design approaches, encompassing circuit design, algorithm-mapping flexibility, inference accuracy, and energy efficiency, are thoroughly discussed.

Bio: Xin Si received his B.S. and Ph.D. degrees in integrated circuit design and integration system from the University of Electronic Science and Technology of China (UESTC), Chengdu, China, in 2016 and 2020, respectively. Since 2021, he has been an Associate Professor in the School of Integrated Circuits at Southeast University (SEU). His current research interests encompass memory, computing-in-memory circuit, and AI Chip designs. He has an extensive publication record, including over 30 conference/journal papers, notably 10 ISSCC papers and 7 JSSC papers. He also serves as an International Technical Program Committee member for IEEE MCSoC and VLSI-DAT.

High Reliability GaN FET Drivers for Next-generation Power Electronics Technology

Abstract: GaN devices become more critical in high-frequency high-power-density power conversion recently, such as half and full-bridge converters as well as synchronous rectifier. Compared to Si power device, the E-mode GaN gains a more negative reverse body diode voltage during dead time, high dV/dt and di/dt when turning on power switch as well as threshold voltage variation. This tutorial introduces the consideration of power GaN gate drive and presents core circuit design. The working principles, advantages/drawbacks and future trend will be discussed.

Bio: Xin Ming  received the M.Sc. and Ph.D. degrees in microelectronics from the University of Electronic Science and Technology of China (UESTC), Chengdu, China, in 2007 and 2012, respectively. From 2013 to 2014, he was a Visiting Scholar with the Center for Power Electronics Systems, Virginia Polytechnic Institute and State University, Blacksburg, USA, where his research activity was ripple-based control circuit design. He is currently a Full Professor with UESTC and ISPSD TPC member. His current research interests include switching power supply, LDO, isolated gate drive and GaN drivers.