Keynote 1

Time: 08:30-09:10 Saturday, October 28

Room: Roadshow Hall, 1F

Session Chair: Yizhe HU

Quantum Computing in Nanoscale CMOS

Robert Bogdan Staszewski

School of Electrical & Electronic Engineering

University College Dublin, Ireland

ABSTRACT: Quantum computing is a new paradigm that exploits fundamental principles of quantum mechanics, such as superposition and entanglement, to tackle problems in mathematics, chemistry and material science that are well beyond the reach of supercomputers. Despite the intensive worldwide race to build a useful quantum computer, it is projected to take decades before reaching the state of useful quantum supremacy. The main challenge is that qubits operate at the atomic level, thus are extremely fragile, and difficult to control and read out. The current state-of-art implements a few dozen magnetic-spin based qubits in a highly specialized technology and cools them down to a few tens of millikelvin. The high cost of cryogenic cooling prevents its widespread use. A companion classical electronic controller, needed to control and read out the qubits, is mostly realized with room-temperature laboratory instrumentation. This makes it bulky and nearly impossible to scale up to the thousands or millions of qubits needed for practical quantum algorithms. We propose a new quantum computer paradigm that exploits the wonderful scaling achievements of mainstream integrated circuits (IC) technology which underpins personal computers and mobile phones. Just like with a small IC chip, where a single nanometer-sized CMOS transistor can be reliably replicated millions of times to build a digital processor, we propose a new structure of a qubit realized as a CMOS-compatible charge-based quantum dot that can be reliably replicated thousands of times to construct a quantum processor. Combined with an on-chip CMOS controller, it will realize a useful quantum computer which can operate at a much higher temperature of 4 kelvin.

BIO: R. Bogdan Staszewski received B.Sc. (summa cum laude), M.Sc. and PhD from University of Texas at Dallas, USA, in 1991, 1992 and 2002, respectively.  From 1991 to 1995 he was with Alcatel in Richardson, Texas. He joined Texas Instruments in Dallas, Texas in 1995. In 1999 he co-started a Digital RF Processor (DRP) group in TI with a mission to invent new digitally intensive approaches to traditional RF functions. Dr. Staszewski served as a CTO of the DRP group between 2007 and 2009. In July 2009 he joined Delft University of Technology in the Netherlands where he is currently a part-time Full Professor. Since Sept. 2014 he has been a Full Professor at University College Dublin (UCD) in Ireland. He has co-authored seven books, 11 book chapters, and over 160 journal and 220 conference publications, and holds 210 issued US patents. His research interests include nanoscale CMOS architectures and circuits for frequency synthesizers, transmitters and receivers, as well as quantum computers. He is a co-founder of a startup company Equal1 Labs aiming at building the first practical CMOS quantum computer. He is an IEEE Fellow and a recipient of IEEE Circuits and Systems Industrial Pioneer Award (https://ieee-cas.org/society-achievement-award-recipients-list).

Keynote 2

Time: 14:00-14:40 Saturday, October 28

Room: Roadshow Hall, 1F

Session Chair: Nan QI

ASIC for AI Embodied in Tomorrow’s Robots - Why and Why Not?

Chik Patrick Yue

The Hong Kong University of Science and Technology, China

ABSTRACT: In the AI era, autonomous driving, connected vehicles, internet of everything (IoE), and humanoid are among the recognized major trend force. They provide the impetus behind new generations of application-specific integrated circuit (ASICs) ranging from compute-in-memory (CIM) and high-bandwidth memory (HBM) to optical interconnect interface and millimetre-wave beam-former. As a ASIC R&D or product design engineer, understanding of the end-market driver and application-specific requirements can greatly improve the circuit design quality and performance, especially for area-constrained and power-sensitive systems. In this seminar, Prof. Patrick Yue will examine the state-of-the-art technologies for mimicking the six human senses with the ultimate goal of enabling multi-robot human collaboration (MRHC). For each of the human senses, the essential technologies may or may not require the development of an ASIC. Using construction robots for building information model (BIM) inspection as an example of MRHC, he will cover indoor navigation, multi-agent systems, 3D perception, and 360° camera image processing.

BIO: C. Patrick Yue received the B.S. degree in Electronic and Computer Engineering (Highest Hons.) from the University of Texas at Austin in 1992, and the M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1994 and 1998, respectively.

Based on his Ph.D. thesis work, he co-founded Atheros Communications in 1998 and contributed to the development and deployment of the world's first IEEE802.11a CMOS Wi-Fi transceiver system-on-chip (SoC). In 2002, he joined Aeluros to work on CMOS high-speed PHY/SerDes IC design and signal integrity issues in chip packaging. Between 2001 and 2003, while working at the start-ups, he served as a Consulting Assistant Professor at Stanford in the EE Department focusing on research in the area of high-frequency CMOS IC design and RF device modeling. In 2003, he joined Carnegie Mellon University in Pittsburgh, PA as an Assistant Professor in the Department of Electrical and Computer Engineering. In 2006, he moved to the University of California, Santa Barbara and was promoted to full professor in 2010. Since 2011, he has been a Professor at the Hong Kong University of Science and Technology (HKUST) in the Department of Electronic and Computer Engineering. From 2014 to 2015, he served as the first Associate Provost for Knowledge Transfer at HKUST. In 2016, he took a sabbatical leave from HKUST to Tsinghua University, Beijing, PRC as a Visiting Chair Professor in the Institute of Microelectronics. In 2017, he founded LiPHY Communications to commercialize visible light communication (VLC) technology for smart building and IoT market. Currently, he is the Director of the HKUST Integrated Circuit Design Center (ICDC), the Optical Wireless Lab (OWL), and the HKUST-Qualcomm Joint Innovation and Research Lab. His research interest includes optical wireless physical layer circuits and systems, high-speed wireline communication SoC, millimeter-wave communication and sensing circuits, indoor positioning and image processing technologies for robotic applications, and edge computing accelerator design for IoT applications.

Keynote 3

Time: 08:30-09:10 Sunday, October 29

Room: Roadshow Hall, 1F

Session Chair: Yuxuan LUO

Redefining SoC Design: Beyond Verilog and Towards Holistic Verification

Nick Tan

Zhejiang University, China

ABSTRACT: Traditional design methodologies for large-scale digital systems or SoCs involve extensive collaboration among professionals with varied expertise, making the process both time-consuming and resource-intensive. This has led to concerns about the ability of academic institutions to produce enough qualified graduates to meet the demands of the IC industry. However, as software increasingly becomes the distinguishing factor in digital systems, there's a growing need to standardize hardware components, with only essential specialized features embedded within a largely uniform platform.

In this presentation, we share our experiences in:

•Adopting Agile Methodologies: Implementing Agile principles in digital system design to enhance flexibility and reusability.

•Holistic Verification: Integrating diverse verification techniques at multiple levels to expedite the verification process. For signal processing and communication, we employ MATLAB/Python code as a benchmark, enabling fuzzy verification of both functionality and performance without the need for bit-to-bit comparisons.

•Utilizing Open-Source SoC Platforms and Chisel: By harnessing the power of open-source SoC platforms and the high-level Chisel language, we've been able to design parameterized systems without the need for manual Verilog coding.

We've successfully applied these innovative methodologies to the design of metering chips, power line communication chips, and MCUs tailored for internet of energy applications. The results are a remarkable efficiency boost of over 5x.

BIO: Nick Tan received his B. Eng. and M. Eng. Degrees from Tsinghua University, Beijing, China, in 1988 and 1991, respectively, and Ph. D. from Linkoping University, Sweden in 1994. He is currently a full professor at Zhejiang University. He also founded Vango Technologies, Inc., and now holds the position of its chairman.

Prior to starting up Vango Technologies, Inc. in China, Dr. Tan was the founder and CEO of AnaLutions, Inc., a design service company in CA, USA. Before that, Dr. Tan worked as a design director for GlobeSpan, NJ, USA (A Bell lab spinoff) and worked at Ericsson’s R&D center in Sweden. He also taught mixed-signal chip design and supervised Ph.D. students at Linköping University, Sweden. Dr. Tan is an accomplished chip designer and researcher. He holds 31 US patents and numerous Chinese patents, has written 3 books and book chapters, and published over 100 papers. He was an editor for the Institute of Electrical and Electronics Engineers (IEEE) and received IEEE outstanding service award. He also received several Chinese awards for innovation and achievements.

Keynote 4

Time: 13:10-13:50 Sunday, October 29

Room: Roadshow Hall, 1F

Session Chair: Zhao ZHANG

Hybrid DC-DC Converter Topologies and Applications

Yan Lu

University of Macau, China

ABSTRACT: With the surging demands for extremely high current at sub-1 V supply voltage level in high performance computing, high density power delivery becomes one of the main bottlenecks for system integration. For the high current applications, high-voltage rails are essential to reduce the IR losses on the power delivery networks. Thus, there is a wide voltage gap between the power bus and the digital supply rails at the point-of-load (PoL), calling for novel power conversion topologies and system architectures. To bridge this gap, switched-capacitor-inductor (SCI) hybrid DC–DC converter has been the hottest topic in the power management IC area in the past 10 years or so. In this talk, we will introduce a few design examples on hybrid DC-DC converters from our research group. Also, we will share several of our observations and design suggestions for future works.

BIO: Yan Lu received the PhD degree in Electronic and Computer Engineering from the Hong Kong University of Science and Technology (HKUST), Hong Kong, China, in 2013.

In 2014, he joined the State Key Laboratory of Analog and Mixed-Signal VLSI at University of Macau, Macau, China, where he is currently an Associate Professor. He has authored/coauthored over 160 peer-reviewed technical papers and two books. His research interests include wireless power transfer circuits and systems, high power density DC-DC converters, integrated voltage regulators, and energy-efficient analog circuits.

He is serving as a TPC Member for ISSCC, Power Management Subcommittee Chair for CICC, and is an IEEE SSCS Distinguished Lecturer 2022-23. Dr. Lu was a recipient of the IEEE Solid-State Circuits Society Pre-Doctoral Achievement Award 2013–2014, the IEEE CAS Society Outstanding Young Author Award in 2017, and the ISSCC 2017 Takuo Sugano Award for Outstanding Far-East Paper.